[PATCH] D90051: AMDGPU/GlobalISel: Add floating point med3 combine for IEEE=false

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Missing tests for f16 and v2f16 cases



================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp:174-175
+
+    // TODO: Add G_FMINNUM_IEEE (requires some additional checks for possible
+    // SNaN input).
+    if (OpcodeTriple.Min == AMDGPU::G_FMINNUM) {
----------------
Might as well handle this now


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp:181-182
+      const SIInstrInfo *TII = MF->getSubtarget<GCNSubtarget>().getInstrInfo();
+      APInt KObits = KO_FPImm.bitcastToAPInt();
+      APInt K1bits = K1_FPImm.bitcastToAPInt();
+      if ((!MRI.hasOneNonDBGUse(K0Def) || TII->isInlineConstant(KObits)) &&
----------------
You can directly pass the APFloat to is the overload of isInlineConstant


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  https://reviews.llvm.org/D90051/new/

https://reviews.llvm.org/D90051