[PATCH] D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

In D89162#2350313 <https://reviews.llvm.org/D89162#2350313>, @nikic wrote:

> @paulwalker-arm There is no need to implement any target-specific support. The legalization outcome will be a simple chain of extracts and fadd/fmuls. It does not need to generate good code, just not assert for any VTs.

Sure,  I think there's been a misunderstanding.  The only target-specific piece we're talking about is the existing `shouldExpandReduction` hook that controls if the code generator will see the `VECREDUCE_SEQ_FADD` to legalise.  So I'm wondering if an acceptable ordering is to allow the lowering of legal `VECREDUCE_SEQ_FADD` operations (which is only what `shouldExpandReduction` will let through) and then we can tackle the type legalisation problem second so that `shouldExpandReduction` can let everything through when SVE is enable (of which they'll already be a test ready and waiting) and leave NEON as it is today.


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  https://reviews.llvm.org/D89162/new/

https://reviews.llvm.org/D89162