[PATCH] D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation

[Nikita Popov via Phabricator via llvm-commits]

nikic added a comment.

@paulwalker-arm There is no need to implement any target-specific support. The legalization outcome will be a simple chain of extracts and fadd/fmuls. It does not need to generate good code, just not assert for any VTs.


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  https://reviews.llvm.org/D89162/new/

https://reviews.llvm.org/D89162