[PATCH] D90029: [ARM][SchedModels] Convert IsLdstsoMinusRegPred to MCSchedPredicate

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 added inline comments.


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Comment at: llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s:166
+# CHECK-NEXT:  1      4     1.00    *      *            pld	[pc, #8]
+# CHECK-NEXT:  1      4     1.00    *      *            pldw	[pc, #-128]
 # CHECK-NEXT:  1      4     1.00    *                   ldr	r5, [r7]
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This should 5 cyc when `IsLdstsoScaledNotOptimalPred` is converted to MC pred


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  https://reviews.llvm.org/D90029/new/

https://reviews.llvm.org/D90029