[PATCH] D90024: [ARM][SchedModels] Get rid of IsLdrAm2ScaledPred
Eugene Leviant via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 23 04:21:28 PDT 2020
evgeny777 created this revision.
evgeny777 added reviewers: andreadb, dmgreen.
Herald added subscribers: danielkiss, gbedwell, hiraditya, kristof.beyls.
Herald added a project: LLVM.
evgeny777 requested review of this revision.
https://reviews.llvm.org/D90024
Files:
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/lib/Target/ARM/ARMScheduleA57.td
llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
Index: llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
===================================================================
--- llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
+++ llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s
@@ -190,7 +190,7 @@
# CHECK-NEXT: 2 4 1.00 * ldrbt r3, [r1], #4
# CHECK-NEXT: 2 4 1.00 * ldrbt r2, [r8], #-8
# CHECK-NEXT: 2 4 1.00 * ldrbt r8, [r7], r6
-# CHECK-NEXT: 2 4 1.00 * ldrbt r1, [r2], -r6, lsl #12
+# CHECK-NEXT: 3 4 1.00 * ldrbt r1, [r2], -r6, lsl #12
# CHECK-NEXT: 2 4 2.00 * ldrd r0, r1, [r5]
# CHECK-NEXT: 2 4 2.00 * ldrd r8, r9, [r2, #15]
# CHECK-NEXT: 4 5 2.00 * ldrd r2, r3, [r9, #32]!
@@ -321,7 +321,7 @@
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6]
-# CHECK-NEXT: - 63.00 63.00 160.00 9.00 55.00 - -
+# CHECK-NEXT: - 63.00 63.00 160.00 10.00 55.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions:
@@ -355,7 +355,7 @@
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r3, [r1], #4
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r2, [r8], #-8
# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r8, [r7], r6
-# CHECK-NEXT: - 0.50 0.50 1.00 - - - - ldrbt r1, [r2], -r6, lsl #12
+# CHECK-NEXT: - 0.50 0.50 1.00 1.00 - - - ldrbt r1, [r2], -r6, lsl #12
# CHECK-NEXT: - - - 2.00 - - - - ldrd r0, r1, [r5]
# CHECK-NEXT: - - - 2.00 - - - - ldrd r8, r9, [r2, #15]
# CHECK-NEXT: - 1.00 1.00 2.00 - - - - ldrd r2, r3, [r9, #32]!
Index: llvm/lib/Target/ARM/ARMScheduleA57.td
===================================================================
--- llvm/lib/Target/ARM/ARMScheduleA57.td
+++ llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -58,10 +58,6 @@
def IsLdstsoMinusRegPredX2 :
SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 2)}]>;
-// Load, scaled register offset
-def IsLdrAm2ScaledPred :
- SchedPredicate<[{TII->isAm2ScaledReg(*MI, 1)}]>;
-
// LDM, base reg in list
def IsLDMBaseRegInListPred : MCSchedPredicate<IsLDMBaseRegInList>;
@@ -467,11 +463,11 @@
"LDRB_POST_REG", "LDR(B?)T_POST$")>;
def A57WriteLdrTRegPost : SchedWriteVariant<[
- SchedVar<IsLdrAm2ScaledPred, [A57Write_4cyc_1I_1L_1M]>,
+ SchedVar<IsLdstsoScaledPredX2, [A57Write_4cyc_1I_1L_1M]>,
SchedVar<NoSchedPred, [A57Write_4cyc_1L_1I]>
]>;
def A57WriteLdrTRegPostWrBack : SchedWriteVariant<[
- SchedVar<IsLdrAm2ScaledPred, [A57WrBackThree]>,
+ SchedVar<IsLdstsoScaledPredX2, [A57WrBackThree]>,
SchedVar<NoSchedPred, [A57WrBackTwo]>
]>;
// 4(3) "I0/I1,L,M" for scaled register, otherwise 4(2) "I0/I1,L"
Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.h
===================================================================
--- llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -184,8 +184,6 @@
bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
// Minus reg for ldstso addr mode
bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const;
- // Scaled register offset in address mode 2
- bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
/// GetInstSize - Returns the size of the specified MachineInstr.
///
Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -647,13 +647,6 @@
return ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
}
-// Load, scaled register offset
-bool ARMBaseInstrInfo::isAm2ScaledReg(const MachineInstr &MI,
- unsigned Op) const {
- unsigned OffImm = MI.getOperand(Op + 2).getImm();
- return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
-}
-
static bool isEligibleForITBlock(const MachineInstr *MI) {
switch (MI->getOpcode()) {
default: return true;
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