[PATCH] D89162: [SVE] Lower fixed length VECREDUCE_SEQ_FADD operation

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally updated this revision to Diff 299971.
cameron.mcinally marked an inline comment as done.
cameron.mcinally added a comment.

Fix 80 column issue. No other changes intended...


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89162/new/

https://reviews.llvm.org/D89162

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D89162.299971.patch
Type: text/x-patch
Size: 18589 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20201022/f16c6cc6/attachment.bin>