[PATCH] D89881: [ARM] Alter t2DoLoopStart to define lr

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Oct 21 06:52:24 PDT 2020 

dmgreen created this revision.
dmgreen added reviewers: SjoerdMeijer, samparker, samtebbs, efriedma, shchenz.
Herald added subscribers: danielkiss, jdoerfert, javed.absar, zzheng, hiraditya, kristof.beyls, qcolombet, MatzeB.
Herald added a project: LLVM.
dmgreen requested review of this revision.

This changes the definition of t2DoLoopStart from

  t2DoLoopStart rGPR

to

  GPRlr = t2DoLoopStart rGPR

This will hopefully mean that low overhead loops are more tied together, and we can more reliably generate loops without reverting or being at the whims of the register allocator.

This is a fairly simple change in itself, but leads to a number of other required alterations.

- The hardware loop pass, if UsePhi is set, now generates loops of the form:

       %start = llvm.start.loop.iterations(%N)
     loop:
       %p = phi [%start], [%dec]
  	 %dec = llvm.loop.decrement.reg(%p, 1)
  	 %c = icmp ne %dec, 0
  	 br %c, loop, exit



- For this a new llvm.start.loop.iterations intrinsic was added, identical to llvm.set.loop.iterations but produces a value as seen above, gluing the loop together more through def-use chains.
- This new instrinsic conceptually produces the same output as input, which is taught to SCEV so that the checks in MVETailPredication are not effected.
- Some minor changes are needed to the ARMLowOverheadLoop pass, but it has been left mostly as before. We should now more reliably be able to tell that the t2DoLoopStart is correct without having to prove it, but t2WhileLoopStart and tail-predicated loops will remain the same.
- And all the tests have been updated. There are a lot of them.

This patch on it's own might cause more trouble that it helps, with more tail-predicated loops being reverted, but some additional patches can hopefully improve upon that to get to something that is better overall.


https://reviews.llvm.org/D89881

Files:
  llvm/docs/LangRef.rst
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/Analysis/ScalarEvolution.cpp
  llvm/lib/CodeGen/HardwareLoops.cpp
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
  llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
  llvm/lib/Target/ARM/MVETailPredication.cpp
  llvm/test/CodeGen/ARM/machine-outliner-unoutlinable.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/clear-maskedinsts.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/cmplx_cong.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-vector-reduce-mve-codegen.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/exitcount.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/extending-loads.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/invariant-qreg.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp-reordered.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-vcmp.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/livereg-no-loop-def.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-cond-iter-count.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/nested.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-invariant.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/regalloc.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/remat-vctp.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/sibling-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-basic.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-const.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-disabled-in-loloops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-narrow.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-pattern-fail.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-reduce.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-widen.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/tp-multiple-vpst.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredicated-max.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-retaining.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-reduce-mve-tail.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-unroll.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir
  llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
  llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
  llvm/test/CodeGen/Thumb2/mve-fma-loops.ll
  llvm/test/CodeGen/Thumb2/mve-fp16convertloops.ll
  llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
  llvm/test/CodeGen/Thumb2/mve-gather-ptrs.ll
  llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
  llvm/test/CodeGen/Thumb2/mve-gather-scatter-ptr-address.ll
  llvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll
  llvm/test/CodeGen/Thumb2/mve-gather-tailpred.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
  llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll
  llvm/test/CodeGen/Thumb2/mve-pred-vctpvpsel.ll
  llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
  llvm/test/CodeGen/Thumb2/mve-scatter-increment.ll
  llvm/test/CodeGen/Thumb2/mve-shifts-scalar.ll
  llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
  llvm/test/CodeGen/Thumb2/mve-vldst4.ll
  llvm/test/Transforms/HardwareLoops/ARM/calls-codegen.ll
  llvm/test/Transforms/HardwareLoops/ARM/calls.ll
  llvm/test/Transforms/HardwareLoops/ARM/fp-emulation.ll
  llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll
  llvm/test/Transforms/HardwareLoops/ARM/structure.ll
  llvm/test/Transforms/HardwareLoops/loop-guards.ll
  llvm/test/Transforms/HardwareLoops/scalar-while.ll

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