[llvm] 782b8f0 - [InstructionSimplify] Precommit more tests for D89317. NFC.
Sjoerd Meijer via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 21 02:25:18 PDT 2020
Author: Sjoerd Meijer
Date: 2020-10-21T10:14:39+01:00
New Revision: 782b8f0d38c954bfe75ab0b7ec3be1eb8d3dbdb2
URL: https://github.com/llvm/llvm-project/commit/782b8f0d38c954bfe75ab0b7ec3be1eb8d3dbdb2
DIFF: https://github.com/llvm/llvm-project/commit/782b8f0d38c954bfe75ab0b7ec3be1eb8d3dbdb2.diff
LOG: [InstructionSimplify] Precommit more tests for D89317. NFC.
Added:
Modified:
llvm/test/Transforms/InstSimplify/compare.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstSimplify/compare.ll b/llvm/test/Transforms/InstSimplify/compare.ll
index a029d0b3c60d..e0817f17df40 100644
--- a/llvm/test/Transforms/InstSimplify/compare.ll
+++ b/llvm/test/Transforms/InstSimplify/compare.ll
@@ -1765,7 +1765,7 @@ define i1 @cmp_through_addrspacecast(i32 addrspace(1)* %p1) {
; Test simplifications for: icmp (X+Y), (X+Z) -> icmp Y,Z
; Test the overflow check when the RHS has NSW set and constant Z is greater
-; or equal than Y, then we know X+Y also can't overflow.
+; than Y, then we know X+Y also can't overflow.
define i1 @icmp_nsw_1(i32 %V) {
; CHECK-LABEL: @icmp_nsw_1(
@@ -1797,6 +1797,130 @@ define i1 @icmp_nsw_2(i32 %V) {
ret i1 %cmp
}
+define i1 @icmp_nsw_22(i32 %V) {
+; CHECK-LABEL: @icmp_nsw_22(
+; CHECK-NEXT: ret i1 true
+;
+ %add5 = add nsw i32 %V, 5
+ %add6 = add nsw i32 %V, 6
+ %cmp = icmp slt i32 %add5, %add6
+ ret i1 %cmp
+}
+
+define i1 @icmp_nsw_23(i32 %V) {
+; CHECK-LABEL: @icmp_nsw_23(
+; CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[V:%.*]], 5
+; CHECK-NEXT: [[ADD6:%.*]] = add i32 [[V]], 6
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD5]], [[ADD6]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %add5 = add nsw i32 %V, 5
+ %add6 = add i32 %V, 6
+ %cmp = icmp slt i32 %add5, %add6
+ ret i1 %cmp
+}
+
+define i1 @icmp_nsw_false(i32 %V) {
+; CHECK-LABEL: @icmp_nsw_false(
+; CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[V:%.*]], 6
+; CHECK-NEXT: [[ADD6:%.*]] = add i32 [[V]], 5
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD5]], [[ADD6]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %add5 = add nsw i32 %V, 6
+ %add6 = add i32 %V, 5
+ %cmp = icmp slt i32 %add5, %add6
+ ret i1 %cmp
+}
+
+define i1 @icmp_nsw_false_2(i32 %V) {
+; CHECK-LABEL: @icmp_nsw_false_2(
+; CHECK-NEXT: ret i1 false
+;
+ %add5 = add nsw i32 %V, 6
+ %add6 = add nsw i32 %V, 5
+ %cmp = icmp slt i32 %add5, %add6
+ ret i1 %cmp
+}
+
+define i1 @icmp_nsw_false_3(i32 %V) {
+; CHECK-LABEL: @icmp_nsw_false_3(
+; CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[V:%.*]], 5
+; CHECK-NEXT: [[ADD6:%.*]] = add i32 [[V]], 5
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD5]], [[ADD6]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %add5 = add nsw i32 %V, 5
+ %add6 = add i32 %V, 5
+ %cmp = icmp slt i32 %add5, %add6
+ ret i1 %cmp
+}
+
+define i1 @icmp_nsw_false_4(i32 %V) {
+; CHECK-LABEL: @icmp_nsw_false_4(
+; CHECK-NEXT: [[ADD5:%.*]] = add i32 [[V:%.*]], 6
+; CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[V]], 5
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD5]], [[ADD6]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %add5 = add i32 %V, 6
+ %add6 = add nsw i32 %V, 5
+ %cmp = icmp slt i32 %add5, %add6
+ ret i1 %cmp
+}
+
+define i1 @icmp_nsw_i8(i8 %V) {
+; CHECK-LABEL: @icmp_nsw_i8(
+; CHECK-NEXT: [[ADD5:%.*]] = add i8 [[V:%.*]], 5
+; CHECK-NEXT: [[ADD6:%.*]] = add nsw i8 [[V]], 6
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[ADD5]], [[ADD6]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %add5 = add i8 %V, 5
+ %add6 = add nsw i8 %V, 6
+ %cmp = icmp slt i8 %add5, %add6
+ ret i1 %cmp
+}
+
+define i1 @icmp_nsw_i16(i16 %V) {
+; CHECK-LABEL: @icmp_nsw_i16(
+; CHECK-NEXT: [[ADD5:%.*]] = add i16 [[V:%.*]], 5
+; CHECK-NEXT: [[ADD6:%.*]] = add nsw i16 [[V]], 6
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[ADD5]], [[ADD6]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %add5 = add i16 %V, 5
+ %add6 = add nsw i16 %V, 6
+ %cmp = icmp slt i16 %add5, %add6
+ ret i1 %cmp
+}
+
+define i1 @icmp_nsw_i64(i64 %V) {
+; CHECK-LABEL: @icmp_nsw_i64(
+; CHECK-NEXT: [[ADD5:%.*]] = add i64 [[V:%.*]], 5
+; CHECK-NEXT: [[ADD6:%.*]] = add nsw i64 [[V]], 6
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[ADD5]], [[ADD6]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %add5 = add i64 %V, 5
+ %add6 = add nsw i64 %V, 6
+ %cmp = icmp slt i64 %add5, %add6
+ ret i1 %cmp
+}
+
+define <4 x i1> @icmp_nsw_vec(<4 x i32> %V) {
+; CHECK-LABEL: @icmp_nsw_vec(
+; CHECK-NEXT: [[ADD5:%.*]] = add <4 x i32> [[V:%.*]], <i32 5, i32 5, i32 5, i32 5>
+; CHECK-NEXT: [[ADD6:%.*]] = add nsw <4 x i32> [[V]], <i32 6, i32 6, i32 6, i32 6>
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt <4 x i32> [[ADD5]], [[ADD6]]
+; CHECK-NEXT: ret <4 x i1> [[CMP]]
+;
+ %add5 = add <4 x i32> %V, <i32 5, i32 5, i32 5, i32 5>
+ %add6 = add nsw <4 x i32> %V, <i32 6, i32 6, i32 6, i32 6>
+ %cmp = icmp slt <4 x i32> %add5, %add6
+ ret <4 x i1> %cmp
+}
+
define i1 @icmp_nsw_3(i32 %V) {
; CHECK-LABEL: @icmp_nsw_3(
; CHECK-NEXT: [[ADD5:%.*]] = add i32 [[V:%.*]], 5
@@ -1878,14 +2002,27 @@ define i1 @icmp_nsw_9(i32 %V1, i32 %V2) {
define i1 @icmp_nsw_10(i32 %V) {
; CHECK-LABEL: @icmp_nsw_10(
; CHECK-NEXT: [[ADD5:%.*]] = add i32 [[V:%.*]], 5
-; CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[V]], 5
+; CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[V]], 6
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[ADD6]], [[ADD5]]
; CHECK-NEXT: ret i1 [[CMP]]
;
%add5 = add i32 %V, 5
- %add6 = add nsw i32 %V, 5
+ %add6 = add nsw i32 %V, 6
%cmp = icmp sgt i32 %add6, %add5
ret i1 %cmp
}
+define i1 @icmp_nsw_11(i32 %V) {
+; CHECK-LABEL: @icmp_nsw_11(
+; CHECK-NEXT: [[ADD5:%.*]] = add i32 [[V:%.*]], -125
+; CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[V]], -99
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD5]], [[ADD6]]
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+ %add5 = add i32 %V, -125
+ %add6 = add nsw i32 %V, -99
+ %cmp = icmp slt i32 %add5, %add6
+ ret i1 %cmp
+}
+
attributes #0 = { null_pointer_is_valid }
More information about the llvm-commits
mailing list