[PATCH] D89642: [VE] Add integer arithmetic vector instructions

[Simon Moll via Phabricator via llvm-commits]

simoll added inline comments.


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Comment at: llvm/lib/Target/VE/VEInstrVec.td:507
+let cx = 1, cx2 = 0 in
+defm PVADDUUP : RVm<"pvaddu.up", 0xc8, V64, I64, VM>;
+let cx = 1, cx2 = 1 in
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kaz7 wrote:
> simoll wrote:
> > Shouldn't the RC register class for `pv.*.up` instructions be `F32`? 
> I remember why I use `I64` here.  This instruction is vector integer add instruction.  I didn't use `F32` here since our `F32` has represented only `f32` values.  It doesn't represent `i32` values.
> 
> However, it may be possible to assign not only `f32` but also `i32` to `F32` register class and use `F32` here.  Similarly, it is also possible to assign both `f32` and `i32` to `I32` register class too since VE has vector floating-point add instruction like "PVFADDLO".
> 
> Let me consider this.
I like your idea of mapping `f32`/`i32` to both `I32` and `F32`. AFAIK, the mapping between types (eg `i32`) and registers (eg `F32`) only matters for isel pattern constraints (custom lowering code is not subject to those constraints).


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  https://reviews.llvm.org/D89642/new/

https://reviews.llvm.org/D89642