[PATCH] D89642: [VE] Add integer arithmetic vector instructions
Kazushi Marukawa via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 19 04:18:55 PDT 2020
kaz7 planned changes to this revision.
kaz7 added a comment.
Add reason and idea.
================
Comment at: llvm/lib/Target/VE/VEInstrVec.td:507
+let cx = 1, cx2 = 0 in
+defm PVADDUUP : RVm<"pvaddu.up", 0xc8, V64, I64, VM>;
+let cx = 1, cx2 = 1 in
----------------
simoll wrote:
> Shouldn't the RC register class for `pv.*.up` instructions be `F32`?
I remember why I use `I64` here. This instruction is vector integer add instruction. I didn't use `F32` here since our `F32` has represented only `f32` values. It doesn't represent `i32` values.
However, it may be possible to assign not only `f32` but also `i32` to `F32` register class and use `F32` here. Similarly, it is also possible to assign both `f32` and `i32` to `I32` register class too since VE has vector floating-point add instruction like "PVFADDLO".
Let me consider this.
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https://reviews.llvm.org/D89642/new/
https://reviews.llvm.org/D89642
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