[PATCH] D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/utils/TableGen/CodeGenSchedule.cpp:1679
+                  [&FromSC](unsigned PIdx) {
+                    return !FromSC.InstRWProcIndices.count(PIdx);
+                  });
----------------
@evgeny777 I'm seeing some asserts on msvc builds inside the count() on ARMGenSubtargetInfo.inc generation


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89114/new/

https://reviews.llvm.org/D89114