[PATCH] D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 added inline comments.


================
Comment at: llvm/test/TableGen/sched-aliases.td:47
+
+def ProcFoo0 : SubtargetFeature<"foo-0", "ARMProcFamily", "foo-0",
+                                "Test Processor #1", []>;
----------------
dmgreen wrote:
> evgeny777 wrote:
> > dmgreen wrote:
> > > Is ProcFoo0 needed?
> > Yes. TableGen won't add model which is not bound to any processor
> Sure, but is the subtarget feature needed? I'm pretty sure you can remove this ProcFoo0 and have the features for "foo-0-model" empty.
Actually it's not. I've removed it in final commit. Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89114/new/

https://reviews.llvm.org/D89114