[PATCH] D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant

Mon Oct 12 03:14:01 PDT 2020

evgeny777 added inline comments.

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Comment at: llvm/test/tools/llvm-mca/ARM/A57-sxtb.s:2
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=armv7 -mcpu=cortex-a57 -instruction-tables < %s | FileCheck %s
+
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dmgreen wrote:
> armv7 -> armv8
> 
> Is this file generated with the script? I would expect more tables at the bottom.
> 
> Can you pre-commit the file and show the differences here.
I've reduced test case to make it easier reviewing it.
Pre-commit seems good idea. See 7102793065f2329a2fde78f32a1f2582dd89b0e7

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89114/new/

https://reviews.llvm.org/D89114