[PATCH] D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 added inline comments.


================
Comment at: llvm/test/TableGen/sched-aliases.td:47
+
+def ProcFoo0 : SubtargetFeature<"foo-0", "ARMProcFamily", "foo-0",
+                                "Test Processor #1", []>;
----------------
dmgreen wrote:
> Is ProcFoo0 needed?
Yes. TableGen won't add model which is not bound to any processor


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  https://reviews.llvm.org/D89114/new/

https://reviews.llvm.org/D89114