[PATCH] D89114: [TableGen][SchedModels] Fix aliasing of SchedWriteVariant

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 created this revision.
evgeny777 added reviewers: atrick, javed.absar, craig.topper, andreadb, dmgreen.
Herald added a subscriber: pengfei.
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evgeny777 requested review of this revision.

Atm this doesn't work:

  def MyWriteV : SchedWriteVariant<...>;
  def : SchedAlias<WriteV, MyWriteV>;

One problem with statements above is that assertion is triggered when `inferFromTransitions` tries to add empty write sequence which triggers assertion in findOrInsertRW.
Another problem is that transition is always added for given scheduling class, even though that class already has InstRW for a same processor.
Patch attempts to fix both of them


https://reviews.llvm.org/D89114

Files:
  llvm/test/TableGen/sched-aliases.td
  llvm/utils/TableGen/CodeGenSchedule.cpp
  llvm/utils/TableGen/CodeGenSchedule.h

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