[llvm] b57451b - [InstCombine] allow vector splats for add+xor with signmask

Sanjay Patel via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 8 08:28:31 PDT 2020


Author: Sanjay Patel
Date: 2020-10-08T10:46:34-04:00
New Revision: b57451b011d39f5a36a8cd6236a49c47692ee89c

URL: https://github.com/llvm/llvm-project/commit/b57451b011d39f5a36a8cd6236a49c47692ee89c
DIFF: https://github.com/llvm/llvm-project/commit/b57451b011d39f5a36a8cd6236a49c47692ee89c.diff

LOG: [InstCombine] allow vector splats for add+xor with signmask

Added: 
    

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
    llvm/test/Transforms/InstCombine/add.ll
    llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
index 00e981686e79..36f9a4258130 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
@@ -924,6 +924,10 @@ Instruction *InstCombinerImpl::foldAddWithConstant(BinaryOperator &Add) {
       C2->isMinSignedValue() && C2->sext(Ty->getScalarSizeInBits()) == *C)
     return CastInst::Create(Instruction::SExt, X, Ty);
 
+  // (X ^ signmask) + C --> (X + (signmask ^ C))
+  if (match(Op0, m_Xor(m_Value(X), m_APInt(C2))) && C2->isSignMask())
+    return BinaryOperator::CreateAdd(X, ConstantInt::get(Ty, *C2 ^ *C));
+
   if (C->isOneValue() && Op0->hasOneUse()) {
     // add (sext i1 X), 1 --> zext (not X)
     // TODO: The smallest IR representation is (select X, 0, 1), and that would
@@ -1300,11 +1304,6 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {
           return BinaryOperator::CreateSub(ConstantExpr::getAdd(XorRHS, CI),
                                            XorLHS);
       }
-      // (X + signmask) + C could have gotten canonicalized to (X^signmask) + C,
-      // transform them into (X + (signmask ^ C))
-      if (XorRHS->getValue().isSignMask())
-        return BinaryOperator::CreateAdd(XorLHS,
-                                         ConstantExpr::getXor(XorRHS, CI));
     }
   }
 

diff  --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll
index 564854c5c5c2..0363cfe3a0d0 100644
--- a/llvm/test/Transforms/InstCombine/add.ll
+++ b/llvm/test/Transforms/InstCombine/add.ll
@@ -423,8 +423,7 @@ define i32 @xor_sign_bit(i32 %x) {
 
 define <2 x i32> @xor_sign_bit_vec_splat(<2 x i32> %x) {
 ; CHECK-LABEL: @xor_sign_bit_vec_splat(
-; CHECK-NEXT:    [[XOR:%.*]] = xor <2 x i32> [[X:%.*]], <i32 -2147483648, i32 -2147483648>
-; CHECK-NEXT:    [[ADD:%.*]] = add <2 x i32> [[XOR]], <i32 42, i32 42>
+; CHECK-NEXT:    [[ADD:%.*]] = add <2 x i32> [[X:%.*]], <i32 -2147483606, i32 -2147483606>
 ; CHECK-NEXT:    ret <2 x i32> [[ADD]]
 ;
   %xor = xor <2 x i32> %x, <i32 2147483648, i32 2147483648>

diff  --git a/llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll b/llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll
index d06651e5a07c..b7edab9d8567 100644
--- a/llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll
+++ b/llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll
@@ -96,8 +96,7 @@ define i32 @n5_is_not_not(i32 %x, i32 %y) {
 
 define <2 x i32> @n5_is_not_not_vec_splat(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @n5_is_not_not_vec_splat(
-; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i32> [[X:%.*]], <i32 -2147483648, i32 -2147483648>
-; CHECK-NEXT:    [[T0_NEG:%.*]] = add <2 x i32> [[TMP1]], <i32 1, i32 1>
+; CHECK-NEXT:    [[T0_NEG:%.*]] = add <2 x i32> [[X:%.*]], <i32 -2147483647, i32 -2147483647>
 ; CHECK-NEXT:    [[T1:%.*]] = add <2 x i32> [[T0_NEG]], [[Y:%.*]]
 ; CHECK-NEXT:    ret <2 x i32> [[T1]]
 ;


        


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