[llvm] 395963c - [InstCombine] add vector splat tests for add of signmask; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2020-10-08T10:46:33-04:00
New Revision: 395963cbe63bba3f2d330dde76957cd900d21f42

URL: https://github.com/llvm/llvm-project/commit/395963cbe63bba3f2d330dde76957cd900d21f42
DIFF: https://github.com/llvm/llvm-project/commit/395963cbe63bba3f2d330dde76957cd900d21f42.diff

LOG: [InstCombine] add vector splat tests for add of signmask; NFC

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/add.ll
    llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll
index 26ce6d2a0475..564854c5c5c2 100644
--- a/llvm/test/Transforms/InstCombine/add.ll
+++ b/llvm/test/Transforms/InstCombine/add.ll
@@ -421,6 +421,17 @@ define i32 @xor_sign_bit(i32 %x) {
   ret i32 %add
 }
 
+define <2 x i32> @xor_sign_bit_vec_splat(<2 x i32> %x) {
+; CHECK-LABEL: @xor_sign_bit_vec_splat(
+; CHECK-NEXT:    [[XOR:%.*]] = xor <2 x i32> [[X:%.*]], <i32 -2147483648, i32 -2147483648>
+; CHECK-NEXT:    [[ADD:%.*]] = add <2 x i32> [[XOR]], <i32 42, i32 42>
+; CHECK-NEXT:    ret <2 x i32> [[ADD]]
+;
+  %xor = xor <2 x i32> %x, <i32 2147483648, i32 2147483648>
+  %add = add <2 x i32> %xor, <i32 42, i32 42>
+  ret <2 x i32> %add
+}
+
 ; No-wrap info allows converting the add to 'or'.
 
 define i8 @add_nsw_signbit(i8 %x) {

diff  --git a/llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll b/llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll
index 49d4ec43768b..d06651e5a07c 100644
--- a/llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll
+++ b/llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll
@@ -93,3 +93,15 @@ define i32 @n5_is_not_not(i32 %x, i32 %y) {
   %t1 = sub i32 %y, %t0
   ret i32 %t1
 }
+
+define <2 x i32> @n5_is_not_not_vec_splat(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @n5_is_not_not_vec_splat(
+; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i32> [[X:%.*]], <i32 -2147483648, i32 -2147483648>
+; CHECK-NEXT:    [[T0_NEG:%.*]] = add <2 x i32> [[TMP1]], <i32 1, i32 1>
+; CHECK-NEXT:    [[T1:%.*]] = add <2 x i32> [[T0_NEG]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[T1]]
+;
+  %t0 = xor <2 x i32> %x, <i32 2147483647, i32 2147483647> ; signmask, but not -1
+  %t1 = sub <2 x i32> %y, %t0
+  ret <2 x i32> %t1
+}