[PATCH] D88742: [AArch64] Identify SAD pattern for v16i8 type
    Vinay Madhusudan via Phabricator via llvm-commits 
    llvm-commits at lists.llvm.org
       
    Thu Oct  8 07:12:25 PDT 2020
    
    
  
mivnay marked an inline comment as done.
mivnay added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11067
+  return true;
+}
+
----------------
RKSimon wrote:
> Any chance we could move some of this pattern matching into SelectionDAG? I'd love to get rid of some of the almost identical code from X86ISelLowering.
I have only handled one of the ABD patterns here. There are [[ https://github.com/llvm/llvm-project/blob/master/llvm/lib/Target/AArch64/AArch64InstrInfo.td#L3817 | more ]] in td files and in other places, which would need a bigger refactoring. I think this is out of purview for this patch and can be filed as an enhancement.
Repository:
  rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88742/new/
https://reviews.llvm.org/D88742
    
    
More information about the llvm-commits
mailing list