[PATCH] D88742: [AArch64] Identify SAD pattern for v16i8 type

[Vinay Madhusudan via Phabricator via llvm-commits]

mivnay added a comment.

In D88742#2318989 <https://reviews.llvm.org/D88742#2318989>, @dmgreen wrote:

> Does this still only handle v16i8?

Currently the patterns written are for v16i8 to v16i16 and v16i8 to v16i32 types. I am not sure what are the other types needed to support along with this as there are **at least 24 more patterns** if we consider signed and floating points excluding the vabdl ones which are already in td files (Reference : https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vabd).

There are 12 type pair possible for unsigned types alone:

1. v8i8  to i16,i32,i64 vector types with same number of elements
2. v16i8 to i16,i32,i64 vector types
3. v4i16 to i32,i64 vector types
4. v8i16 to i32, i64 vector types
5. v2i32 to v2i64 vector type
6. v4i32 to v4i64 vector type

I have handled the current patterns to solve the bug mentioned in the ticket. Which other types do you have in mind?


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https://reviews.llvm.org/D88742