[PATCH] D88742: [AArch64] Identify SAD pattern for v16i8 type

Wed Oct 7 02:09:26 PDT 2020

dmgreen added a comment.

In D88742#2314735 <https://reviews.llvm.org/D88742#2314735>, @mivnay wrote:

>> What part of sadb are you worried about? I thought they could be treated the same, given you are extended from enough extra bits. But I may be mistaken, they can be somewhat difficult.
>
> I am worried about the semantics of sabd instruction especially about `v16i32 (sub(sext(v16i8), sext(v16i8))) to v16i32 sext(sub(v16i8, v16i8))` part. Can this be looked at later once my other patches are through?

The return type of the abd is positive unsigned, so I think if turning it into `v16i32 zext(sabd(v16i8, v16i8))` should be valid? But it's worth testing that, I may be mistaken..

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