[PATCH] D88742: [AArch64] Identify SAD pattern for v16i8 type

Tue Oct 6 09:49:25 PDT 2020

mivnay added a comment.

> What part of sadb are you worried about? I thought they could be treated the same, given you are extended from enough extra bits. But I may be mistaken, they can be somewhat difficult.

I am worried about the semantics of sabd instruction especially about `v16i32 (sub(sext(v16i8), sext(v16i8))) to v16i32 sext(sub(v16i8, v16i8))` part. Can this be looked at later once my other patches are through?

> Can D88897 <https://reviews.llvm.org/D88897> be folder back into here now?

There seems to be more issues <https://reviews.llvm.org/harbormaster/unit/view/177149/> for adding SABD ISD node. Since it is a separate patch now, can this one move forward?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88742/new/

https://reviews.llvm.org/D88742