[llvm] 5d6d8a2 - [RISCV] Add SiFive cores to the CPU option
Evandro Menezes via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 5 16:41:05 PDT 2020
Hi, Douglas.
I noticed it. Will fix it soon.
Thank you,
__
Evandro Menezes ◊ SiFive ◊ Austin, TX
> On Oct 5, 2020, at 18:39, Yung, Douglas via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>
> Hi Evandro,
>
> The change you made in clang/test/Driver/riscv-cpus.c is failing on at least one upstream bot, can you take a look?
>
> http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/38179
>
> <stdin>:7:338: note: scanning from here
> "/b/1/clang-x86_64-debian-fast/llvm.obj/bin/clang-12" "-cc1" "-triple" "riscv64" "-emit-obj" "-mrelax-all" "--mrelax-relocations" "-disable-free" "-main-file-name" "riscv-cpus.c" "-mrelocation-model" "static" "-mframe-pointer=all" "-fmath-errno" "-fno-rounding-math" "-mconstructor-aliases" "-nostdsysteminc" "-target-cpu" "sifive-e76" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+c" "-target-feature" "+relax" "-target-feature" "-save-restore" "-target-abi" "ilp32" "-msmall-data-limit" "8" "-fno-split-dwarf-inlining" "-debugger-tuning=gdb" "-resource-dir" "/b/1/clang-x86_64-debian-fast/llvm.obj/lib/clang/12.0.0" "-internal-isystem" "include" "-fdebug-compilation-dir" "/b/1/clang-x86_64-debian-fast/llvm.obj/tools/clang/test/Driver" "-ferror-limit" "19" "-fno-signed-char" "-fgnuc-version=4.2.1" "-faddrsig" "-o" "riscv-cpus.o" "-x" "c" "/b/1/clang-x86_64-debian-fast/llvm.src/clang/test/Driver/riscv-cpus.c"
> ^
>
> Input file: <stdin>
> Check file: /b/1/clang-x86_64-debian-fast/llvm.src/clang/test/Driver/riscv-cpus.c
>
> -dump-input=help explains the following input dump.
>
> Input was:
> <<<<<<
> 1: clang version 12.0.0 (/b/1/clang-x86_64-debian-fast/llvm.src/clang 5d6d8a2769b3a91fd65b125c2cda64ea27a894bf)
> 2: Target: riscv64
> 3: Thread model: posix
> 4: InstalledDir: /b/1/clang-x86_64-debian-fast/llvm.obj/bin
> 5: clang-12: error: the clang compiler does not support '-mcpu=sifive-e76'
> 6: (in-process)
> 7: "/b/1/clang-x86_64-debian-fast/llvm.obj/bin/clang-12" "-cc1" "-triple" "riscv64" "-emit-obj" "-mrelax-all" "--mrelax-relocations" "-disable-free" "-main-file-name" "riscv-cpus.c" "-mrelocation-model" "static" "-mframe-pointer=all" "-fmath-errno" "-fno-rounding-math" "-mconstructor-aliases" "-nostdsysteminc" "-target-cpu" "sifive-e76" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+c" "-target-feature" "+relax" "-target-feature" "-save-restore" "-target-abi" "ilp32" "-msmall-data-limit" "8" "-fno-split-dwarf-inlining" "-debugger-tuning=gdb" "-resource-dir" "/b/1/clang-x86_64-debian-fast/llvm.obj/lib/clang/12.0.0" "-internal-isystem" "include" "-fdebug-compilation-dir" "/b/1/clang-x86_64-debian-fast/llvm.obj/tools/clang/test/Driver" "-ferror-limit" "19" "-fno-signed-char" "-fgnuc-version=4.2.1" "-faddrsig" "-o" "riscv-cpus.o" "-x" "c" "/b/1/clang-x86_64-debian-fast/llvm.src/clang/test/Driver/riscv-cpus.c"
> check:34
>
>
> Douglas Yung
>
> -----Original Message-----
> From: llvm-commits <llvm-commits-bounces at lists.llvm.org> On Behalf Of Evandro Menezes via llvm-commits
> Sent: Monday, October 5, 2020 14:05
> To: llvm-commits at lists.llvm.org
> Subject: [llvm] 5d6d8a2 - [RISCV] Add SiFive cores to the CPU option
>
>
> Author: Evandro Menezes
> Date: 2020-10-05T15:50:57-05:00
> New Revision: 5d6d8a2769b3a91fd65b125c2cda64ea27a894bf
>
> URL: https://github.com/llvm/llvm-project/commit/5d6d8a2769b3a91fd65b125c2cda64ea27a894bf
> DIFF: https://github.com/llvm/llvm-project/commit/5d6d8a2769b3a91fd65b125c2cda64ea27a894bf.diff
>
> LOG: [RISCV] Add SiFive cores to the CPU option
>
> Add the SiFive cores E76 and U74 using the SiFive 7 series microarchitecture.
>
> Differential Revision: https://reviews.llvm.org/D88759
>
> Added:
>
>
> Modified:
> clang/test/Driver/riscv-cpus.c
> clang/test/Misc/target-invalid-cpu-note.c
> llvm/include/llvm/Support/RISCVTargetParser.def
> llvm/lib/Target/RISCV/RISCV.td
>
> Removed:
>
>
>
> ################################################################################
> diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 15cd212e4fb4..2bd0b26f3caf 100644
> --- a/clang/test/Driver/riscv-cpus.c
> +++ b/clang/test/Driver/riscv-cpus.c
> @@ -7,12 +7,12 @@
> // MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64"
> // MCPU-ROCKET64: "-target-feature" "+64bit"
>
> -// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=bullet-rv32 | FileCheck -check-prefix=MCPU-BULLET32 %s -// MCPU-BULLET32: "-nostdsysteminc" "-target-cpu" "bullet-rv32"
> +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-7-rv32 |
> +FileCheck -check-prefix=MCPU-SIFIVE7-32 %s // MCPU-SIFIVE7-32: "-nostdsysteminc" "-target-cpu" "sifive-7-rv32"
>
> -// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=bullet-rv64 | FileCheck -check-prefix=MCPU-BULLET64 %s -// MCPU-BULLET64: "-nostdsysteminc" "-target-cpu" "bullet-rv64"
> -// MCPU-BULLET64: "-target-feature" "+64bit"
> +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-7-rv64 |
> +FileCheck -check-prefix=MCPU-SIFIVE7-64 %s // MCPU-SIFIVE7-64: "-nostdsysteminc" "-target-cpu" "sifive-7-rv64"
> +// MCPU-SIFIVE7-64: "-target-feature" "+64bit"
>
> // mcpu with default march
> // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s @@ -28,6 +28,20 @@ // MCPU-ABI-SIFIVE-U54: "-target-feature" "+c" "-target-feature" "+64bit"
> // MCPU-ABI-SIFIVE-U54: "-target-abi" "lp64"
>
> +// mcpu with default march
> +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e76 |
> +FileCheck -check-prefix=MCPU-SIFIVE-E76 %s // MCPU-SIFIVE-E76: "-nostdsysteminc" "-target-cpu" "sifive-e76"
> +// MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
> +// MCPU-SIFIVE-E76: "-target-feature" "+c"
> +// MCPU-SIFIVE-E76: "-target-abi" "lp64d"
> +
> +// mcpu with mabi option
> +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u74
> +-mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s // MCPU-ABI-SIFIVE-U74: "-nostdsysteminc" "-target-cpu" "sifive-u74"
> +// MCPU-ABI-SIFIVE-U74: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
> +// MCPU-ABI-SIFIVE-U74: "-target-feature" "+c" "-target-feature" "+64bit"
> +// MCPU-ABI-SIFIVE-U74: "-target-abi" "lp64"
> +
> // march overwrite mcpu's default march // RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -march=rv32imc | FileCheck -check-prefix=MCPU-MARCH %s // MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" "+m" "-target-feature" "+c"
>
> diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
> index efcecbbc4726..309cb637c0c5 100644
> --- a/clang/test/Misc/target-invalid-cpu-note.c
> +++ b/clang/test/Misc/target-invalid-cpu-note.c
> @@ -191,8 +191,8 @@
>
> // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32 // RISCV32: error: unknown target CPU 'not-a-cpu'
> -// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, bullet-rv32, sifive-e31
> +// RISCV32: note: valid target CPU values are: generic-rv32,
> +rocket-rv32, sifive-7-rv32, sifive-e31, sifive-e76
>
> // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu'
> -// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, bullet-rv64, sifive-u54
> +// RISCV64: note: valid target CPU values are: generic-rv64,
> +rocket-rv64, sifive-7-rv64, sifive-u54, sifive-u74
>
> diff --git a/llvm/include/llvm/Support/RISCVTargetParser.def b/llvm/include/llvm/Support/RISCVTargetParser.def
> index e6003a4fdebb..a63874fa5dd0 100644
> --- a/llvm/include/llvm/Support/RISCVTargetParser.def
> +++ b/llvm/include/llvm/Support/RISCVTargetParser.def
> @@ -7,9 +7,11 @@ PROC(GENERIC_RV32, {"generic-rv32"}, FK_NONE, {""}) PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {""}) PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""}) PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""}) -PROC(BULLET_RV32, {"bullet-rv32"}, FK_NONE, {""}) -PROC(BULLET_RV64, {"bullet-rv64"}, FK_64BIT, {""})
> +PROC(BULLET_RV32, {"sifive-7-rv32"}, FK_NONE, {""}) PROC(BULLET_RV64,
> +{"sifive-7-rv64"}, FK_64BIT, {""})
> PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"}) PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
> +PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
> +PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
>
> #undef PROC
>
> diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 240dad1ed5ca..1b2c471faac8 100644
> --- a/llvm/lib/Target/RISCV/RISCV.td
> +++ b/llvm/lib/Target/RISCV/RISCV.td
> @@ -228,8 +228,8 @@ def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; def : ProcessorModel<"rocket-rv32", RocketModel, []>; def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
>
> -def : ProcessorModel<"bullet-rv32", BulletModel, []>; -def : ProcessorModel<"bullet-rv64", BulletModel, [Feature64Bit]>;
> +def : ProcessorModel<"sifive-7-rv32", BulletModel, []>; def :
> +ProcessorModel<"sifive-7-rv64", BulletModel, [Feature64Bit]>;
>
> def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM,
> FeatureStdExtA, @@ -242,6 +242,18 @@ def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
> FeatureStdExtD,
> FeatureStdExtC]>;
>
> +def : ProcessorModel<"sifive-e76", BulletModel, [FeatureStdExtM,
> + FeatureStdExtA,
> + FeatureStdExtF,
> + FeatureStdExtC]>;
> +
> +def : ProcessorModel<"sifive-u74", BulletModel, [Feature64Bit,
> + FeatureStdExtM,
> + FeatureStdExtA,
> + FeatureStdExtF,
> + FeatureStdExtD,
> + FeatureStdExtC]>;
> +
> //===----------------------------------------------------------------------===//
> // Define the RISC-V target.
> //===----------------------------------------------------------------------===//
>
>
>
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