<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">Hi, Douglas.<div class=""><br class=""></div><div class="">I noticed it. Will fix it soon.</div><div class=""><br class=""></div><div class="">Thank you,</div><div class=""><br class=""></div><div class=""><div class=""><div dir="auto" style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><div dir="auto" style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><div dir="auto" style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><div dir="auto" style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><div>__ </div><div>Evandro Menezes ◊ SiFive ◊ Austin, TX</div><div class=""><br class=""></div></div></div></div></div></div><div><br class=""><blockquote type="cite" class=""><div class="">On Oct 5, 2020, at 18:39, Yung, Douglas via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="">Hi Evandro,<br class=""><br class="">The change you made in clang/test/Driver/riscv-cpus.c is failing on at least one upstream bot, can you take a look?<br class=""><br class=""><a href="http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/38179" class="">http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/38179</a><br class=""><br class=""><stdin>:7:338: note: scanning from here<br class=""> "/b/1/clang-x86_64-debian-fast/llvm.obj/bin/clang-12" "-cc1" "-triple" "riscv64" "-emit-obj" "-mrelax-all" "--mrelax-relocations" "-disable-free" "-main-file-name" "riscv-cpus.c" "-mrelocation-model" "static" "-mframe-pointer=all" "-fmath-errno" "-fno-rounding-math" "-mconstructor-aliases" "-nostdsysteminc" "-target-cpu" "sifive-e76" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+c" "-target-feature" "+relax" "-target-feature" "-save-restore" "-target-abi" "ilp32" "-msmall-data-limit" "8" "-fno-split-dwarf-inlining" "-debugger-tuning=gdb" "-resource-dir" "/b/1/clang-x86_64-debian-fast/llvm.obj/lib/clang/12.0.0" "-internal-isystem" "include" "-fdebug-compilation-dir" "/b/1/clang-x86_64-debian-fast/llvm.obj/tools/clang/test/Driver" "-ferror-limit" "19" "-fno-signed-char" "-fgnuc-version=4.2.1" "-faddrsig" "-o" "riscv-cpus.o" "-x" "c" "/b/1/clang-x86_64-debian-fast/llvm.src/clang/test/Driver/riscv-cpus.c"<br class=""> ^<br class=""><br class="">Input file: <stdin><br class="">Check file: /b/1/clang-x86_64-debian-fast/llvm.src/clang/test/Driver/riscv-cpus.c<br class=""><br class="">-dump-input=help explains the following input dump.<br class=""><br class="">Input was:<br class=""><<<<<<<br class=""> 1: clang version 12.0.0 (/b/1/clang-x86_64-debian-fast/llvm.src/clang 5d6d8a2769b3a91fd65b125c2cda64ea27a894bf)<br class=""> 2: Target: riscv64<br class=""> 3: Thread model: posix<br class=""> 4: InstalledDir: /b/1/clang-x86_64-debian-fast/llvm.obj/bin<br class=""> 5: clang-12: error: the clang compiler does not support '-mcpu=sifive-e76'<br class=""> 6: (in-process)<br class=""> 7: "/b/1/clang-x86_64-debian-fast/llvm.obj/bin/clang-12" "-cc1" "-triple" "riscv64" "-emit-obj" "-mrelax-all" "--mrelax-relocations" "-disable-free" "-main-file-name" "riscv-cpus.c" "-mrelocation-model" "static" "-mframe-pointer=all" "-fmath-errno" "-fno-rounding-math" "-mconstructor-aliases" "-nostdsysteminc" "-target-cpu" "sifive-e76" "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+c" "-target-feature" "+relax" "-target-feature" "-save-restore" "-target-abi" "ilp32" "-msmall-data-limit" "8" "-fno-split-dwarf-inlining" "-debugger-tuning=gdb" "-resource-dir" "/b/1/clang-x86_64-debian-fast/llvm.obj/lib/clang/12.0.0" "-internal-isystem" "include" "-fdebug-compilation-dir" "/b/1/clang-x86_64-debian-fast/llvm.obj/tools/clang/test/Driver" "-ferror-limit" "19" "-fno-signed-char" "-fgnuc-version=4.2.1" "-faddrsig" "-o" "riscv-cpus.o" "-x" "c" "/b/1/clang-x86_64-debian-fast/llvm.src/clang/test/Driver/riscv-cpus.c"<br class="">check:34<br class=""><br class=""><br class="">Douglas Yung<br class=""><br class="">-----Original Message-----<br class="">From: llvm-commits <llvm-commits-bounces@lists.llvm.org> On Behalf Of Evandro Menezes via llvm-commits<br class="">Sent: Monday, October 5, 2020 14:05<br class="">To: llvm-commits@lists.llvm.org<br class="">Subject: [llvm] 5d6d8a2 - [RISCV] Add SiFive cores to the CPU option<br class=""><br class=""><br class="">Author: Evandro Menezes<br class="">Date: 2020-10-05T15:50:57-05:00<br class="">New Revision: 5d6d8a2769b3a91fd65b125c2cda64ea27a894bf<br class=""><br class="">URL: https://github.com/llvm/llvm-project/commit/5d6d8a2769b3a91fd65b125c2cda64ea27a894bf<br class="">DIFF: https://github.com/llvm/llvm-project/commit/5d6d8a2769b3a91fd65b125c2cda64ea27a894bf.diff<br class=""><br class="">LOG: [RISCV] Add SiFive cores to the CPU option<br class=""><br class="">Add the SiFive cores E76 and U74 using the SiFive 7 series microarchitecture.<br class=""><br class="">Differential Revision: https://reviews.llvm.org/D88759<br class=""><br class="">Added: <br class=""><br class=""><br class="">Modified: <br class=""> clang/test/Driver/riscv-cpus.c<br class=""> clang/test/Misc/target-invalid-cpu-note.c<br class=""> llvm/include/llvm/Support/RISCVTargetParser.def<br class=""> llvm/lib/Target/RISCV/RISCV.td<br class=""><br class="">Removed: <br class=""><br class=""><br class=""><br class="">################################################################################<br class="">diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 15cd212e4fb4..2bd0b26f3caf 100644<br class="">--- a/clang/test/Driver/riscv-cpus.c<br class="">+++ b/clang/test/Driver/riscv-cpus.c<br class="">@@ -7,12 +7,12 @@<br class=""> // MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64"<br class=""> // MCPU-ROCKET64: "-target-feature" "+64bit"<br class=""><br class="">-// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=bullet-rv32 | FileCheck -check-prefix=MCPU-BULLET32 %s -// MCPU-BULLET32: "-nostdsysteminc" "-target-cpu" "bullet-rv32"<br class="">+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-7-rv32 | <br class="">+FileCheck -check-prefix=MCPU-SIFIVE7-32 %s // MCPU-SIFIVE7-32: "-nostdsysteminc" "-target-cpu" "sifive-7-rv32"<br class=""><br class="">-// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=bullet-rv64 | FileCheck -check-prefix=MCPU-BULLET64 %s -// MCPU-BULLET64: "-nostdsysteminc" "-target-cpu" "bullet-rv64"<br class="">-// MCPU-BULLET64: "-target-feature" "+64bit"<br class="">+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-7-rv64 | <br class="">+FileCheck -check-prefix=MCPU-SIFIVE7-64 %s // MCPU-SIFIVE7-64: "-nostdsysteminc" "-target-cpu" "sifive-7-rv64"<br class="">+// MCPU-SIFIVE7-64: "-target-feature" "+64bit"<br class=""><br class=""> // mcpu with default march<br class=""> // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s @@ -28,6 +28,20 @@ // MCPU-ABI-SIFIVE-U54: "-target-feature" "+c" "-target-feature" "+64bit"<br class=""> // MCPU-ABI-SIFIVE-U54: "-target-abi" "lp64"<br class=""><br class="">+// mcpu with default march<br class="">+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e76 | <br class="">+FileCheck -check-prefix=MCPU-SIFIVE-E76 %s // MCPU-SIFIVE-E76: "-nostdsysteminc" "-target-cpu" "sifive-e76"<br class="">+// MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"<br class="">+// MCPU-SIFIVE-E76: "-target-feature" "+c"<br class="">+// MCPU-SIFIVE-E76: "-target-abi" "lp64d"<br class="">+<br class="">+// mcpu with mabi option<br class="">+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 <br class="">+-mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s // MCPU-ABI-SIFIVE-U74: "-nostdsysteminc" "-target-cpu" "sifive-u74"<br class="">+// MCPU-ABI-SIFIVE-U74: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"<br class="">+// MCPU-ABI-SIFIVE-U74: "-target-feature" "+c" "-target-feature" "+64bit"<br class="">+// MCPU-ABI-SIFIVE-U74: "-target-abi" "lp64"<br class="">+<br class=""> // march overwrite mcpu's default march // RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -march=rv32imc | FileCheck -check-prefix=MCPU-MARCH %s // MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" "+m" "-target-feature" "+c"<br class=""><br class="">diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c<br class="">index efcecbbc4726..309cb637c0c5 100644<br class="">--- a/clang/test/Misc/target-invalid-cpu-note.c<br class="">+++ b/clang/test/Misc/target-invalid-cpu-note.c<br class="">@@ -191,8 +191,8 @@<br class=""><br class=""> // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32 // RISCV32: error: unknown target CPU 'not-a-cpu'<br class="">-// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, bullet-rv32, sifive-e31<br class="">+// RISCV32: note: valid target CPU values are: generic-rv32, <br class="">+rocket-rv32, sifive-7-rv32, sifive-e31, sifive-e76<br class=""><br class=""> // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu'<br class="">-// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, bullet-rv64, sifive-u54<br class="">+// RISCV64: note: valid target CPU values are: generic-rv64, <br class="">+rocket-rv64, sifive-7-rv64, sifive-u54, sifive-u74<br class=""><br class="">diff --git a/llvm/include/llvm/Support/RISCVTargetParser.def b/llvm/include/llvm/Support/RISCVTargetParser.def<br class="">index e6003a4fdebb..a63874fa5dd0 100644<br class="">--- a/llvm/include/llvm/Support/RISCVTargetParser.def<br class="">+++ b/llvm/include/llvm/Support/RISCVTargetParser.def<br class="">@@ -7,9 +7,11 @@ PROC(GENERIC_RV32, {"generic-rv32"}, FK_NONE, {""}) PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {""}) PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""}) PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""}) -PROC(BULLET_RV32, {"bullet-rv32"}, FK_NONE, {""}) -PROC(BULLET_RV64, {"bullet-rv64"}, FK_64BIT, {""})<br class="">+PROC(BULLET_RV32, {"sifive-7-rv32"}, FK_NONE, {""}) PROC(BULLET_RV64, <br class="">+{"sifive-7-rv64"}, FK_64BIT, {""})<br class=""> PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"}) PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})<br class="">+PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"}) <br class="">+PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})<br class=""><br class=""> #undef PROC<br class=""><br class="">diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 240dad1ed5ca..1b2c471faac8 100644<br class="">--- a/llvm/lib/Target/RISCV/RISCV.td<br class="">+++ b/llvm/lib/Target/RISCV/RISCV.td<br class="">@@ -228,8 +228,8 @@ def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; def : ProcessorModel<"rocket-rv32", RocketModel, []>; def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;<br class=""><br class="">-def : ProcessorModel<"bullet-rv32", BulletModel, []>; -def : ProcessorModel<"bullet-rv64", BulletModel, [Feature64Bit]>;<br class="">+def : ProcessorModel<"sifive-7-rv32", BulletModel, []>; def : <br class="">+ProcessorModel<"sifive-7-rv64", BulletModel, [Feature64Bit]>;<br class=""><br class=""> def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM,<br class=""> FeatureStdExtA, @@ -242,6 +242,18 @@ def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,<br class=""> FeatureStdExtD,<br class=""> FeatureStdExtC]>;<br class=""><br class="">+def : ProcessorModel<"sifive-e76", BulletModel, [FeatureStdExtM,<br class="">+ FeatureStdExtA,<br class="">+ FeatureStdExtF,<br class="">+ FeatureStdExtC]>;<br class="">+<br class="">+def : ProcessorModel<"sifive-u74", BulletModel, [Feature64Bit,<br class="">+ FeatureStdExtM,<br class="">+ FeatureStdExtA,<br class="">+ FeatureStdExtF,<br class="">+ FeatureStdExtD,<br class="">+ FeatureStdExtC]>;<br class="">+<br class=""> //===----------------------------------------------------------------------===//<br class=""> // Define the RISC-V target.<br class=""> //===----------------------------------------------------------------------===//<br class=""><br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class="">llvm-commits@lists.llvm.org<br class="">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits<br class="">_______________________________________________<br class="">llvm-commits mailing list<br class="">llvm-commits@lists.llvm.org<br class="">https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits<br class=""></div></div></blockquote></div><br class=""><div class="">
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