[llvm] 64b879a - [TableGen][GlobalISel] add handling of nested *_SUBREG

[Mikael Holmen via llvm-commits]

Author: Gabriel Hjort Åkerlund
Date: 2020-10-05T10:42:18+02:00
New Revision: 64b879ae2a8a4a4e541404c19d96d18c4aed810e

URL: https://github.com/llvm/llvm-project/commit/64b879ae2a8a4a4e541404c19d96d18c4aed810e
DIFF: https://github.com/llvm/llvm-project/commit/64b879ae2a8a4a4e541404c19d96d18c4aed810e.diff

LOG: [TableGen][GlobalISel] add handling of nested *_SUBREG

When nesting INSERT_SUBREG and EXTRACT_SUBREG, GlobalISelEmitter would
fail to find the register class of the nested node. This patch fixes
that for registers with subregs.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D88487

Added: 
    llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td

Modified: 
    llvm/utils/TableGen/GlobalISelEmitter.cpp

Removed: 
    


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diff  --git a/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td b/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
new file mode 100644
index 000000000000..c48c82aa142a
--- /dev/null
+++ b/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
@@ -0,0 +1,66 @@
+// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+
+include "llvm/Target/Target.td"
+include "GlobalISelEmitterCommon.td"
+
+let Namespace = "MyTarget" in {
+
+def lo8  : SubRegIndex<8>;
+def hi8  : SubRegIndex<8, 8>;
+def lo16 : SubRegIndex<16>;
+def hi16 : SubRegIndex<16, 16>;
+
+def a0bl : Register<"a0bl">;
+def a0bh : Register<"a0bh">;
+def a0wh : Register<"a0wh">;
+
+} // Namespace = "MyTarget"
+
+def a0wl: RegisterWithSubRegs<"a0", [a0bh, a0bl]> {
+  let SubRegIndices = [hi8, lo8];
+  let CoveredBySubRegs = 1;
+}
+
+def a0: RegisterWithSubRegs<"a0", [a0wh, a0wl]> {
+  let SubRegIndices = [hi16, lo16];
+  let CoveredBySubRegs = 1;
+}
+
+def A0b : RegisterClass<"MyTarget",  [i8],  8, (add a0bl)>;
+def A0w : RegisterClass<"MyTarget", [i16], 16, (add a0wl)>;
+def A0  : RegisterClass<"MyTarget", [i32], 32, (add a0)>;
+
+// CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
+// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ANYEXT,
+// CHECK-NEXT: // MIs[0] dst
+// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
+// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::A0RegClassID,
+// CHECK-NEXT: // MIs[0] src
+// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8,
+// CHECK-NEXT: // (anyext:{ *:[i16] } i8:{ *:[i8] }:$src)  =>  (EXTRACT_SUBREG:{ *:[i16] } (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), A0b:{ *:[i8] }:$src, lo8:{ *:[i32] }), lo16:{ *:[i32] })
+// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
+// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF,
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG,
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
+// CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*Imm*/3,
+// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, MyTarget::A0RegClassID,
+// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, MyTarget::A0RegClassID,
+// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, MyTarget::A0bRegClassID,
+// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+// CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, MyTarget::lo16,
+// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
+// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, MyTarget::A0wRegClassID,
+// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, MyTarget::A0RegClassID,
+def : Pat<(i16 (anyext i8:$src)),
+          (i16 (EXTRACT_SUBREG
+                 (i32 (INSERT_SUBREG
+                        (i32 (IMPLICIT_DEF)),
+                        A0b:$src,
+                        lo8)),
+                 lo16))>;

diff  --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 752ca109d1cb..ec7d20692096 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -4951,6 +4951,17 @@ GlobalISelEmitter::inferRegClassFromPattern(TreePatternNode *N) {
       return None;
     return getRegClassFromLeaf(RCChild);
   }
+  if (InstName == "INSERT_SUBREG") {
+    TreePatternNode *Child0 = N->getChild(0);
+    assert(Child0->getNumTypes() == 1 && "Unexpected number of types!");
+    const TypeSetByHwMode &VTy = Child0->getExtType(0);
+    return inferSuperRegisterClassForNode(VTy, Child0, N->getChild(2));
+  }
+  if (InstName == "EXTRACT_SUBREG") {
+    assert(N->getNumTypes() == 1 && "Unexpected number of types!");
+    const TypeSetByHwMode &VTy = N->getExtType(0);
+    return inferSuperRegisterClass(VTy, N->getChild(1));
+  }
 
   // Handle destination record types that we can safely infer a register class
   // from.