[PATCH] D88759: [RISCV] Add SiFive cores to the CPU option

[Jim Lin via Phabricator via llvm-commits]

Jim added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCV.td:257
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It should only have one blank line.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88759/new/

https://reviews.llvm.org/D88759