[llvm] 39fc4a0 - [X86] Move ENCODEKEY128/256 handling from lowering to selection.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 3 18:47:54 PDT 2020
Author: Craig Topper
Date: 2020-10-03T18:44:53-07:00
New Revision: 39fc4a0b0af69772ee360b5f729b1ec453217793
URL: https://github.com/llvm/llvm-project/commit/39fc4a0b0af69772ee360b5f729b1ec453217793
DIFF: https://github.com/llvm/llvm-project/commit/39fc4a0b0af69772ee360b5f729b1ec453217793.diff
LOG: [X86] Move ENCODEKEY128/256 handling from lowering to selection.
We should avoid emitting MachineSDNodes from lowering.
We can use the the implicit def handling in InstrEmitter to avoid
manually copying from each xmm result register. We only need to
manually emit the copies for the implicit uses.
Added:
Modified:
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 0d80bde5f717..356a3f7228de 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -4488,6 +4488,38 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
switch (Opcode) {
default: break;
+ case ISD::INTRINSIC_W_CHAIN: {
+ unsigned IntNo = Node->getConstantOperandVal(1);
+ switch (IntNo) {
+ default: break;
+ case Intrinsic::x86_encodekey128:
+ case Intrinsic::x86_encodekey256: {
+ if (!Subtarget->hasKL())
+ break;
+
+ unsigned Opcode;
+ switch (IntNo) {
+ default: llvm_unreachable("Impossible intrinsic");
+ case Intrinsic::x86_encodekey128: Opcode = X86::ENCODEKEY128; break;
+ case Intrinsic::x86_encodekey256: Opcode = X86::ENCODEKEY256; break;
+ }
+
+ SDValue Chain = Node->getOperand(0);
+ Chain = CurDAG->getCopyToReg(Chain, dl, X86::XMM0, Node->getOperand(3),
+ SDValue());
+ if (Opcode == X86::ENCODEKEY256)
+ Chain = CurDAG->getCopyToReg(Chain, dl, X86::XMM1, Node->getOperand(4),
+ Chain.getValue(1));
+
+ MachineSDNode *Res = CurDAG->getMachineNode(
+ Opcode, dl, Node->getVTList(),
+ {Node->getOperand(2), Chain, Chain.getValue(1)});
+ ReplaceNode(Node, Res);
+ return;
+ }
+ }
+ break;
+ }
case ISD::INTRINSIC_VOID: {
unsigned IntNo = Node->getConstantOperandVal(1);
switch (IntNo) {
@@ -5737,6 +5769,9 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
case X86ISD::AESDECWIDE128KL:
case X86ISD::AESENCWIDE256KL:
case X86ISD::AESDECWIDE256KL: {
+ if (!Subtarget->hasWIDEKL())
+ break;
+
unsigned Opcode;
switch (Node->getOpcode()) {
default:
@@ -5779,11 +5814,8 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
Chain = CurDAG->getCopyToReg(Chain, dl, X86::XMM7, Node->getOperand(9),
Chain.getValue(1));
- SDVTList VTs = CurDAG->getVTList(
- {MVT::i32, MVT::v2i64, MVT::v2i64, MVT::v2i64, MVT::v2i64, MVT::v2i64,
- MVT::v2i64, MVT::v2i64, MVT::v2i64, MVT::Other});
SDNode *Res = CurDAG->getMachineNode(
- Opcode, dl, VTs,
+ Opcode, dl, Node->getVTList(),
{Base, Scale, Index, Disp, Segment, Chain, Chain.getValue(1)});
ReplaceNode(Node, Res);
return;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a49847d9ed29..72cddbb1f83e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -25952,67 +25952,6 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget &Subtarget,
return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
Operation.getValue(1));
}
- case Intrinsic::x86_encodekey128:
- case Intrinsic::x86_encodekey256: {
- SDLoc DL(Op);
- SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other, MVT::Glue);
- SDValue Chain = Op.getOperand(0);
- bool IsEK256 = false;
- Chain = DAG.getCopyToReg(Chain, DL, X86::XMM0, Op->getOperand(3),
- SDValue());
-
- unsigned Opcode;
-
- switch (IntNo) {
- default: llvm_unreachable("Impossible intrinsic");
- case Intrinsic::x86_encodekey128:
- Opcode = X86::ENCODEKEY128;
- break;
- case Intrinsic::x86_encodekey256:
- Opcode = X86::ENCODEKEY256;
- Chain = DAG.getCopyToReg(Chain, DL, X86::XMM1, Op->getOperand(4),
- Chain.getValue(1));
- IsEK256 = true;
- break;
- }
-
- SDNode *Res = DAG.getMachineNode(Opcode, DL, VTs,
- {Op.getOperand(2), Chain,
- Chain.getValue(1)});
-
- Chain = SDValue(Res, 1);
-
- SDValue XMM0 = DAG.getCopyFromReg(Chain, DL, X86::XMM0, MVT::v16i8,
- SDValue(Res, 2));
- SDValue XMM1 = DAG.getCopyFromReg(XMM0.getValue(1), DL, X86::XMM1,
- MVT::v16i8, XMM0.getValue(2));
- SDValue XMM2 = DAG.getCopyFromReg(XMM1.getValue(1), DL, X86::XMM2,
- MVT::v16i8, XMM1.getValue(2));
- SDValue XMM3, XMM4;
- if (IsEK256) {
- XMM3 = DAG.getCopyFromReg(XMM2.getValue(1), DL, X86::XMM3,
- MVT::v16i8, XMM2.getValue(2));
- XMM4 = DAG.getCopyFromReg(XMM3.getValue(1), DL, X86::XMM4,
- MVT::v16i8, XMM3.getValue(2));
- } else {
- XMM4 = DAG.getCopyFromReg(XMM2.getValue(1), DL, X86::XMM4,
- MVT::v16i8, XMM2.getValue(2));
- }
- SDValue XMM5 = DAG.getCopyFromReg(XMM4.getValue(1), DL, X86::XMM5,
- MVT::v16i8, XMM4.getValue(2));
- SDValue XMM6 = DAG.getCopyFromReg(XMM5.getValue(1), DL, X86::XMM6,
- MVT::v16i8, XMM5.getValue(2));
-
- if (IsEK256) {
- return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(),
- {SDValue(Res, 0),
- XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, Chain});
- } else {
- return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(),
- {SDValue(Res, 0),
- XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, Chain});
- }
- }
case Intrinsic::x86_aesenc128kl:
case Intrinsic::x86_aesdec128kl:
case Intrinsic::x86_aesenc256kl:
More information about the llvm-commits
mailing list