[llvm] 7f3da48 - [X86] Remove X86ISD::MWAITX_DAG. Just match the intrinsic to the custom inserter pseudo instruction during isel.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 3 18:47:52 PDT 2020
Author: Craig Topper
Date: 2020-10-03T18:44:53-07:00
New Revision: 7f3da488852b157e456333cc40048526409d4592
URL: https://github.com/llvm/llvm-project/commit/7f3da488852b157e456333cc40048526409d4592
DIFF: https://github.com/llvm/llvm-project/commit/7f3da488852b157e456333cc40048526409d4592.diff
LOG: [X86] Remove X86ISD::MWAITX_DAG. Just match the intrinsic to the custom inserter pseudo instruction during isel.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.h
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86InstrInfo.td
llvm/test/tools/llvm-mca/X86/Generic/resources-mwaitx.s
llvm/test/tools/llvm-mca/X86/Znver1/resources-mwaitx.s
llvm/test/tools/llvm-mca/X86/Znver2/resources-mwaitx.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e526a1dd58eb..a49847d9ed29 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -25952,20 +25952,6 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget &Subtarget,
return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
Operation.getValue(1));
}
- case Intrinsic::x86_mwaitx: {
- // If the current function needs the base pointer, RBX,
- // we shouldn't use mwaitx directly.
- // Indeed the lowering of that instruction will clobber
- // that register and since RBX will be a reserved register
- // the register allocator will not make sure its value will
- // be properly saved and restored around this live-range.
- SDLoc dl(Op);
- unsigned Opcode = X86ISD::MWAITX_DAG;
- SDValue Chain = DAG.getNode(Opcode, dl, MVT::Other,
- {Op->getOperand(0), Op->getOperand(2),
- Op->getOperand(3), Op->getOperand(4)});
- return Chain;
- }
case Intrinsic::x86_encodekey128:
case Intrinsic::x86_encodekey256: {
SDLoc DL(Op);
@@ -30848,7 +30834,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(LCMPXCHG16_DAG)
NODE_NAME_CASE(LCMPXCHG8_SAVE_EBX_DAG)
NODE_NAME_CASE(LCMPXCHG16_SAVE_RBX_DAG)
- NODE_NAME_CASE(MWAITX_DAG)
NODE_NAME_CASE(LADD)
NODE_NAME_CASE(LSUB)
NODE_NAME_CASE(LOR)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 9f231be78191..00ead0c09cce 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -710,9 +710,6 @@ namespace llvm {
// For avx512-vp2intersect
VP2INTERSECT,
- // Mwaitx builtin is lowered to this if the base pointer needs saving.
- MWAITX_DAG,
-
// Key locker nodes that produce flags.
AESENC128KL,
AESDEC128KL,
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index 4f81c271386c..9e6a5fb934de 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -930,7 +930,7 @@ def MWAITX :
I<0, Pseudo, (outs),
(ins GR32:$ecx, GR32:$eax, GR32:$ebx),
"mwaitx",
- [(X86mwaitx GR32:$ecx, GR32:$eax, GR32:$ebx)]>;
+ [(int_x86_mwaitx GR32:$ecx, GR32:$eax, GR32:$ebx)]>;
}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 3a3d141854a1..47de7d609855 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -77,9 +77,6 @@ def SDTX86caspairSaveRbx16 : SDTypeProfile<1, 3,
[SDTCisVT<0, i64>, SDTCisPtrTy<1>,
SDTCisVT<2, i64>, SDTCisVT<3, i64>]>;
-def SDTX86mwaitx : SDTypeProfile<0, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
- SDTCisVT<2, i32>]>;
-
def SDTLockBinaryArithWithFlags : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
SDTCisPtrTy<1>,
SDTCisInt<2>]>;
@@ -192,10 +189,6 @@ def X86cas16save_rbx : SDNode<"X86ISD::LCMPXCHG16_SAVE_RBX_DAG",
[SDNPHasChain, SDNPInGlue, SDNPOutGlue,
SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
-def X86mwaitx : SDNode<"X86ISD::MWAITX_DAG", SDTX86mwaitx,
- [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
- SDNPMayLoad]>;
-
def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret,
@@ -2811,8 +2804,7 @@ let SchedRW = [ WriteSystem ] in {
let Uses = [ ECX, EAX, EBX ] in {
def MWAITXrrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx",
- [(int_x86_mwaitx ECX, EAX, EBX)]>,
- TB, Requires<[ HasMWAITX ]>;
+ []>, TB, Requires<[ HasMWAITX ]>;
}
} // SchedRW
diff --git a/llvm/test/tools/llvm-mca/X86/Generic/resources-mwaitx.s b/llvm/test/tools/llvm-mca/X86/Generic/resources-mwaitx.s
index 517b283dafac..5f8125f3b192 100644
--- a/llvm/test/tools/llvm-mca/X86/Generic/resources-mwaitx.s
+++ b/llvm/test/tools/llvm-mca/X86/Generic/resources-mwaitx.s
@@ -14,7 +14,7 @@ mwaitx
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 100 0.33 U monitorx
-# CHECK-NEXT: 1 100 0.33 * * U mwaitx
+# CHECK-NEXT: 1 100 0.33 U mwaitx
# CHECK: Resources:
# CHECK-NEXT: [0] - SBDivider
diff --git a/llvm/test/tools/llvm-mca/X86/Znver1/resources-mwaitx.s b/llvm/test/tools/llvm-mca/X86/Znver1/resources-mwaitx.s
index c296b21d7541..4aafec738b59 100644
--- a/llvm/test/tools/llvm-mca/X86/Znver1/resources-mwaitx.s
+++ b/llvm/test/tools/llvm-mca/X86/Znver1/resources-mwaitx.s
@@ -14,7 +14,7 @@ mwaitx
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 100 0.25 U monitorx
-# CHECK-NEXT: 1 100 0.25 * * U mwaitx
+# CHECK-NEXT: 1 100 0.25 U mwaitx
# CHECK: Resources:
# CHECK-NEXT: [0] - ZnAGU0
diff --git a/llvm/test/tools/llvm-mca/X86/Znver2/resources-mwaitx.s b/llvm/test/tools/llvm-mca/X86/Znver2/resources-mwaitx.s
index 6c2b8153c26a..d33ccce03391 100644
--- a/llvm/test/tools/llvm-mca/X86/Znver2/resources-mwaitx.s
+++ b/llvm/test/tools/llvm-mca/X86/Znver2/resources-mwaitx.s
@@ -14,7 +14,7 @@ mwaitx
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 100 0.25 U monitorx
-# CHECK-NEXT: 1 100 0.25 * * U mwaitx
+# CHECK-NEXT: 1 100 0.25 U mwaitx
# CHECK: Resources:
# CHECK-NEXT: [0] - Zn2AGU0
More information about the llvm-commits
mailing list