[PATCH] D88676: [PPC][AIX] Add vector callee saved registers for AIX extended vector ABI

[Xiangling Liao via Phabricator via llvm-commits]

Xiangling_L added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/aix-csr-vector.ll:2
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN: FileCheck --check-prefix=MIR32 %s
----------------
sfertile wrote:
> Minor nit: align this with the first argument in the preceeding line.
The ABI mentioned AIX5.3 is the first AIX release to enable vector programming, and there are arch like pwr4 is not compatible with altivec. Since this is our first altivec patch, it looks it's the right place to add `report_fatal_error` for arch level which doesn't support altivec.


================
Comment at: llvm/test/CodeGen/PowerPC/aix-csr-vector.ll:3
+; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN: FileCheck --check-prefix=MIR32 %s
+
----------------
sfertile wrote:
>  I'm not sure the formatting we have adopted for the tests, but I think subsequent commands were to be indented by 2? @Xiangling_L or @DiggerLin  might know better, I think it was on one of their reviews where I saw it mentioned.
The original formatting comment is here: https://reviews.llvm.org/D78929#inline-740137


================
Comment at: llvm/test/CodeGen/PowerPC/aix-csr-vector.ll:222
+; ASM64-DAG:      lxvd2x 52, {{[0-9]+}}, {{[0-9]+}}                         # 16-byte Folded Reload
+; ASM64:      blr
----------------
Could you also add a testcase showing how csr FPR/GPR interact with nonvolatile VR?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88676/new/

https://reviews.llvm.org/D88676