[PATCH] D88663: [AArch64] Use TargetRegisterClass::hasSubClassEq in tryToFindRegisterToRename

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp:813
+        if (TRI->getMinimalPhysRegClass(OriginalReg)
+                ->hasSubClassEq(TRI->getMinimalPhysRegClass(SubOrSuper)))
           return SubOrSuper;
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I don't think this does what you want.  Suppose we had a separate register class for every single AArch64 register.  Then this would fail unless OriginalReg and SubOrSuper are equal, I think.

Maybe instead of `TRI->getMinimalPhysRegClass(OriginalReg)`, we can use MachineInstr::getRegClassConstraint?


================
Comment at: llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp:1414
+          TRI->sub_and_superregs_inclusive(PR), [C, TRI](MCPhysReg SubOrSuper) {
+            return C->hasSubClassEq(TRI->getMinimalPhysRegClass(SubOrSuper));
+          });
----------------
`C->hasSubClassEq(TRI->getMinimalPhysRegClass(SubOrSuper));` seems like a really awkward way to write `C->contains(SubOrSuper)`


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D88663/new/

https://reviews.llvm.org/D88663