[PATCH] D88663: [AArch64] Use TargetRegisterClass::hasSubClassEq in tryToFindRegisterToRename

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, efriedma, fhahn, paquette.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.
c-rhodes requested review of this revision.

When renaming store operands for pairing in the load/store optimizer it
tries to find an available register from the minimal physical register
class of the original register. For each register it compares the
equality of minimal physical register class of all sub/super registers
with the minimal physical register class of the original register.

Simply checking for register class equality can break once additional
register classes are added, as was the case when adding:

  def foo : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)>

which broke:

  CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
  CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
  CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
  CodeGen/AArch64/stp-opt-with-renaming.mir

Since the introduction of the register class above, the rename register
in test1 of the reserved regs test changed from x12 to x18. The reason
for this is the minimal physical register class of x12 (as well as
x13-x15) and its sub/super registers no longer matches that of x9
(GPR64noip_and_tcGPR64).

This patch changes the register class comparison to use hasSubClassEq.

It's worth mentioning the parameter passing registers (r0-r7) could be now be
used as rename registers since the GPR32arg and GPR64arg register classes are
subclasses of the minimal physical register class for x8 for example. I'm not
entirely sure if we want to exclude those registers, if so maybe we could
explicitly exclude those register classes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D88663

Files:
  llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  llvm/test/CodeGen/AArch64/arm64-abi-varargs.ll
  llvm/test/CodeGen/AArch64/machine-outliner.ll
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming-debug.mir
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

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