[PATCH] D88642: [AArch64] Match the windows canonical callee saved register order [alternative implementation]

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> This keeps the logic mostly straightforward compared to before, but gives some amount of mismatch between the stack objects generated by PrologEpilogInserter, which are laid out from top to bottom in the original register order.

It seems worth adding a little extra code to avoid this.



================
Comment at: llvm/lib/Target/AArch64/AArch64FrameLowering.cpp:2092
 
   for (unsigned i = 0; i < Count; ++i) {
     RegPairInfo RPI;
----------------
When I said "iterate backwards" in the other review, I was more thinking of changing this for loop to iterate over CSI starting from Count - 1, not reversing the stores relative to the frame objects.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D88642/new/

https://reviews.llvm.org/D88642