[llvm] c6b18cf - [RISCV] Use the extensions in the canonical order (NFC)

[Evandro Menezes via llvm-commits]

Author: Evandro Menezes
Date: 2020-09-29T20:03:02-05:00
New Revision: c6b18cf9672bca4f61bb3ef401173742068e46ea

URL: https://github.com/llvm/llvm-project/commit/c6b18cf9672bca4f61bb3ef401173742068e46ea
DIFF: https://github.com/llvm/llvm-project/commit/c6b18cf9672bca4f61bb3ef401173742068e46ea.diff

LOG: [RISCV] Use the extensions in the canonical order (NFC)

Use the ISA extensions for specific processors in the conventional canonical order.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCV.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 578b393dc879..66eda3ba360c 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -231,16 +231,16 @@ def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
 def : ProcessorModel<"bullet-rv32", BulletModel, []>;
 def : ProcessorModel<"bullet-rv64", BulletModel, [Feature64Bit]>;
 
-def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtA,
-                                                 FeatureStdExtC,
-                                                 FeatureStdExtM]>;
+def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM,
+                                                 FeatureStdExtA,
+                                                 FeatureStdExtC]>;
 
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
+                                                 FeatureStdExtM,
+                                                 FeatureStdExtF,
                                                  FeatureStdExtA,
-                                                 FeatureStdExtC,
                                                  FeatureStdExtD,
-                                                 FeatureStdExtF,
-                                                 FeatureStdExtM]>;
+                                                 FeatureStdExtC]>;
 
 //===----------------------------------------------------------------------===//
 // Define the RISC-V target.