[PATCH] D87046: [PPC] Do not emit extswsli in 32BIT mode when using -mcpu=pwr9

[Sean Fertile via Phabricator via llvm-commits]

sfertile added a comment.

In D87046#2288155 <https://reviews.llvm.org/D87046#2288155>, @ZarkoCA wrote:

> In D87046#2285772 <https://reviews.llvm.org/D87046#2285772>, @sfertile wrote:
>
>> Does `PPCMIPeephole::combineSEXTAndSHL` have a similar problem that needs to be addressed?
>
> I thought so, but it looks like that function is only called when `PPCMIPeephole::simplifyCode` sees an `RLDICR` Opcode which is a 64Bit only instruction.  So it looks like we avoid this problem there.

Thanks for looking into it.



================
Comment at: llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll:15
+
+; CHECK-LABEL:     .a
+
----------------
Is the `.` character treated as a regex? Neither 32-bit or 64-bit assembly will produce `.a` in the assembly, both produce `a:`, but the test works, so I am clearly missing something.


================
Comment at: llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll:18
+; 32BIT:           srawi [[REG1:[0-9]+]], [[REG2:[0-9]+]]
+; 32BIT-NEXT:      rotlwi [[REG3:[0-9]+]], [[REG2]], [[REG4:[0-9]+]]
+; 32BIT-NEXT:      slwi [[REG2]], [[REG2]], [[REG4]]
----------------
Xiangling_L wrote:
> I am suggesting to use eg. `[[REG3:[0-9]+]]` to match register, use `{{[0-9]+}}` to match numbers. Or since `8` is hardcoded in the IR, we don't need to worry about this value will change in the assembly .
> 
> For example, 
> 
> ```
> rotlwi [[REG3:[0-9]+]], [[REG2]], 8
> 
> ```
+1, and same for the ME/MB fields of the rlwimi instruction.


================
Comment at: llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll:22
+
+; 64BIT:           extswsli {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} 
----------------
Real minor nit, but there is a trailing space at the end of this line.


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