[PATCH] D87046: [PPC] Do not emit extswsli in 32BIT mode when using -mcpu=pwr9

[Xiangling Liao via Phabricator via llvm-commits]

Xiangling_L added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll:17
+
+; 32BIT:           srawi [[REG1:[0-9]+]], [[REG2:[0-9]+]]
+; 32BIT-NEXT:      rotlwi [[REG3:[0-9]+]], [[REG2]], [[REG4:[0-9]+]]
----------------
It seems, you missed matching the third part of srawi instruction. Any reason of doing so?


================
Comment at: llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll:18
+; 32BIT:           srawi [[REG1:[0-9]+]], [[REG2:[0-9]+]]
+; 32BIT-NEXT:      rotlwi [[REG3:[0-9]+]], [[REG2]], [[REG4:[0-9]+]]
+; 32BIT-NEXT:      slwi [[REG2]], [[REG2]], [[REG4]]
----------------
I am suggesting to use eg. `[[REG3:[0-9]+]]` to match register, use `{{[0-9]+}}` to match numbers. Or since `8` is hardcoded in the IR, we don't need to worry about this value will change in the assembly .

For example, 

```
rotlwi [[REG3:[0-9]+]], [[REG2]], 8

```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87046/new/

https://reviews.llvm.org/D87046