[PATCH] D87796: [SVE][WIP] Lower fixed length VECREDUCE_ADD to Scalable

[Cameron McInally via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGdb40a7434429: [SVE] Lower fixed length ISD::VECREDUCE_ADD to Scalable (authored by cameron.mcinally).

Changed prior to commit:
  https://reviews.llvm.org/D87796?vs=293465&id=293720#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87796/new/

https://reviews.llvm.org/D87796

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D87796.293720.patch
Type: text/x-patch
Size: 16852 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200923/d247cdda/attachment.bin>