[PATCH] D87900: [ARM] Remove MVEDomain from VLDR/STR of P0
Sam Parker via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 18 05:43:55 PDT 2020
samparker created this revision.
samparker added reviewers: dmgreen, SjoerdMeijer, samtebbs.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.
samparker requested review of this revision.
Remove the domain from the instructions and create a shouldInspect helper for LowOverheadLoops which queries it or a vpr operand.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D87900
Files:
llvm/lib/Target/ARM/ARMInstrVFP.td
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
Index: llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -82,6 +82,12 @@
return MI->findRegisterDefOperandIdx(ARM::VPR) != -1;
}
+static bool shouldInspect(MachineInstr &MI) {
+ uint64_t Domain = MI.getDesc().TSFlags & ARMII::DomainMask;
+ return Domain == ARMII::DomainMVE ||
+ isVectorPredicate(&MI) || isVectorPredicated(&MI);
+}
+
namespace {
using InstSet = SmallPtrSetImpl<MachineInstr *>;
@@ -801,9 +807,7 @@
MachineBasicBlock *Header = ML.getHeader();
for (auto &MI : *Header) {
- const MCInstrDesc &MCID = MI.getDesc();
- uint64_t Flags = MCID.TSFlags;
- if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
+ if (!shouldInspect(MI))
continue;
if (isVCTP(&MI) || isVPTOpcode(MI.getOpcode()))
@@ -972,9 +976,7 @@
if (CannotTailPredicate)
return false;
- const MCInstrDesc &MCID = MI->getDesc();
- uint64_t Flags = MCID.TSFlags;
- if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
+ if (!shouldInspect(*MI))
return true;
if (MI->getOpcode() == ARM::MVE_VPSEL ||
@@ -996,6 +998,7 @@
// Inspect uses first so that any instructions that alter the VPR don't
// alter the predicate upon themselves.
+ const MCInstrDesc &MCID = MI->getDesc();
bool IsUse = false;
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
const MachineOperand &MO = MI->getOperand(i);
@@ -1014,6 +1017,7 @@
// If we find an instruction that has been marked as not valid for tail
// predication, only allow the instruction if it's contained within a valid
// VPT block.
+ uint64_t Flags = MCID.TSFlags;
if ((Flags & ARMII::ValidForTailPredication) == 0) {
LLVM_DEBUG(if (!IsUse)
dbgs() << "ARM Loops: Can't tail predicate: " << *MI);
Index: llvm/lib/Target/ARM/ARMInstrVFP.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrVFP.td
+++ llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -2490,8 +2490,7 @@
"vmrs", "\t$Rt, fpcxts", []>;
}
- let Predicates = [HasV8_1MMainline, HasMVEInt],
- D=MVEDomain, validForTailPredication=1 in {
+ let Predicates = [HasV8_1MMainline, HasMVEInt] in {
// System level VPR/P0 -> GPR
let Uses = [VPR] in
def VMRS_VPR : MovFromVFP<0b1100 /* vpr */, (outs GPR:$Rt), (ins),
@@ -2847,7 +2846,7 @@
}
let Predicates = [HasV8_1MMainline, HasMVEInt],
- D=MVEDomain, validForTailPredication=1 in {
+ validForTailPredication=1 in {
let Uses = [VPR] in {
defm VSTR_VPR : vfp_vstrldr_sysreg<0b0,0b1100, "vpr">;
}
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