[PATCH] D87231: [AArch64] Match pairwise add/fadd pattern

[Sanne Wouda via Phabricator via llvm-commits]

sanwou01 marked an inline comment as done.
sanwou01 added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11627
+                         DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Other,
+                                     DAG.getConstant(0, SDLoc(N), MVT::i64)),
+                         DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Other,
----------------
dmgreen wrote:
> SDLoc(N) -> DL
Huh, I missed those, thanks! This'll be fixed when I land this change.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87231/new/

https://reviews.llvm.org/D87231