[PATCH] D87621: [AMDGPU] Add XDL resource to scheduling model

[Austin Kerbow via Phabricator via llvm-commits]

kerbowa added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SISchedule.td:107-109
+def HWXDL   : ProcResource<1> { // MFMA CU
+  let BufferSize = 0;
+}
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foad wrote:
> As I understand it, from reading comments in MCSchedule.h and TargetSchedule.td, you have to set BufferSize = 0 to model instructions that immediately consume a resource for one or more cycles. It would be useful to do this for some VALU instructions, e.g. some transcendental instructions, that take more than one cycle to issue (on gfx10).
> 
> What I don't understand is, for a normal single-cycle issue (on gfx10) SALU or VALU instruction, should we use BufferSize = 0 or 1 ? What practical difference does it make?
The conclusion I started to come to when working on this was that a BufferSize of 0 makes sense for most resources given our hardware. A BufferSize of 1 is used to model pipelines where a bubble could be introduced if instructions with a data dependency require the same resource. I'm not sure if there is any practical difference for normal VALU or SALU Ops though.

We would also need to model these types of non-nop hazards in the post-RA scheduler. I started working on some infrastructure for that.


Repository:
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  https://reviews.llvm.org/D87621/new/

https://reviews.llvm.org/D87621