[PATCH] D87231: [AArch64] Match pairwise add/fadd pattern

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

Thanks for making the extra fp16 patterns too. LGTM



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11627
+                         DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Other,
+                                     DAG.getConstant(0, SDLoc(N), MVT::i64)),
+                         DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Other,
----------------
SDLoc(N) -> DL


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87231/new/

https://reviews.llvm.org/D87231