[PATCH] D87430: [ARM] Add heuristic to avoid lowering calls to blx for Thumb1 in ARMTargetLowering::LowerCall

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:2261
+      // Hardcoded for now.
+      unsigned nRegs = 7;
+
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dmgreen wrote:
> Hmm. Not sure. Perhaps this can use something like getRegClassFor(MVT::i32)->getNumRegs()? It's still probably a very rough estimate of allocatable registers.
I don't understand the intent here.

In Thumb1 mode, there are four callee-save registers that are considered allocatable: r4-r7.  We must use one of them to store the address of an indirect call.  (We could potentially use high registers, but that isn't implemented.)  None of them are ever used to pass arguments.  Given that, why does the number of arguments to the function matter? Why does the number of caller-save registers matter?


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https://reviews.llvm.org/D87430