[PATCH] D87351: AMDGPU/GlobalISel/Emitter Recognize additional 'same operand checks'

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic added a comment.

min3/max3 patterns are handled in combiner, inducing med3 patterns with constants. Patch imports med3 isel patterns: `min(max(a, b), max(min(a, b), c))` but they need some combines/legalize fixes to be selected. From new imports only V_FRACT can be selected at the moment.



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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir:27-28
     ; CHECK: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]
     ; CHECK: %12:vreg_64 = nofpexcept V_ADD_F64 0, [[COPY3]], 1, [[COPY4]], 0, 0, implicit $mode, implicit $exec
-    ; CHECK: %13:vreg_64 = nofpexcept V_FLOOR_F64_e64 0, %12, 0, 0, implicit $mode, implicit $exec
-    ; CHECK: %15:vreg_64 = nofpexcept V_ADD_F64 0, %12, 1, %13, 0, 0, implicit $mode, implicit $exec
+    ; CHECK: %15:vreg_64 = nofpexcept V_FRACT_F64_e64 0, %12, 0, 0, implicit $mode, implicit $exec
     ; CHECK: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
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arsenm wrote:
> Is this pattern really correct? It should probably be moved into a combine instead of a selection pattern if so
It is correctly selected  since -enable-unsafe-fp-math flag was on.


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