[PATCH] D87236: [X86][SSE2] Use smarter instruction patterns for lowering UMIN/UMAX with v8i16 and SMIN/SMAX with v16i8.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

@RKSimon Can we match the horizontal reductions early during DAG combine and insert the sign bit flip at the top and bottom of the tree and rewrite the intermediate min/maxes to the other type? That would hide them from the lowering code changes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87236/new/

https://reviews.llvm.org/D87236