[PATCH] D87215: [SelectionDAG][X86][ARM] Teach ExpandIntRes_ABS to use sra+add+xor expansion when ADDCARRY is supported.

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGda79b1eecc65: [SelectionDAG][X86][ARM] Teach ExpandIntRes_ABS to use sra+add+xor expansion… (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D87215?vs=290157&id=290338#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87215/new/

https://reviews.llvm.org/D87215

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/Thumb2/mve-abs.ll
  llvm/test/CodeGen/X86/abs.ll
  llvm/test/CodeGen/X86/iabs.ll

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