[PATCH] D86548: [SVE][CodeGen] Legalisation of truncate for scalable vectors

[Kerry McLaughlin via Phabricator via llvm-commits]

kmclaughlin marked an inline comment as not done.
kmclaughlin added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:4681
 
 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
   SDLoc dl(N);
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efriedma wrote:
> How do we end up here? I guess we split the truncate into two truncs, and then concatenate the two truncates?
That's correct, we end up here when the result type is legal but the operand needs to be split, e.g.
`trunc <vscale x 4 x i64> %in to <vscale x 4 x i32>`
In this example we try to split the trunc in two truncates with return types of `<vscale x 2 x i32>`, and concatenate them.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8971
+      SDValue LoVec0;
+      if (Vec0.getOpcode() == AArch64ISD::UZP1 && Vec0->getOperand(1).isUndef())
+        LoVec0 = Vec0->getOperand(0);
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efriedma wrote:
> Is the `Vec0->getOperand(1).isUndef()` check actually necessary?
> 
> Can we have the same set of checks for optimizing the "other" half in the low and high cases?  Some of them won't be immediately useful, but it helps make the logic more clear.
I changed this slightly so that we are using the same set of checks on both halves, and removed the extra `isUndef()` check as I don't think it was necessary here.


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https://reviews.llvm.org/D86548