[PATCH] D85956: [AARCH64][RegisterCoalescer] clang miscompiles zero-extension to long long

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir:3
+# RUN: -run-pass simple-register-coalescing | FileCheck %s
+
+--- |
----------------
Add a comment explaining the test?

You don't need -O1 


================
Comment at: llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir:4-11
+--- |
+  @c = local_unnamed_addr global i8 -1, align 4
+
+  define i64 @bug_e(i32 %i32) local_unnamed_addr {
+  ret i64 0
+  }
+...
----------------
Don't need the IR section


================
Comment at: llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir:23-36
+
+    %4:gpr32 = ANDWrr %0, %1
+    %5:gpr64 = SUBREG_TO_REG 0, killed %4, %subreg.sub_32
+    %6:gpr64 = SUBSXrr %3, killed %5, implicit-def $nzcv
+    Bcc 1, %bb.2, implicit $nzcv
+    B %bb.1
+
----------------
I think you can trim most of these instructions


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85956/new/

https://reviews.llvm.org/D85956