[llvm] 75d159f - [LegalizeTypes] Add ROTL/ROTR to ScalarizeVectorResult.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2020-08-26T14:42:57+01:00
New Revision: 75d159f924868ec93e3008b04b637412b64de29e

URL: https://github.com/llvm/llvm-project/commit/75d159f924868ec93e3008b04b637412b64de29e
DIFF: https://github.com/llvm/llvm-project/commit/75d159f924868ec93e3008b04b637412b64de29e.diff

LOG: [LegalizeTypes] Add ROTL/ROTR to ScalarizeVectorResult.

We can scalarize these just like any other binary operation.

Fixes https://bugs.llvm.org/show_bug.cgi?id=47303 caused by D77152.

Differential Revision: https://reviews.llvm.org/D86601

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 44cc077f2988..f8f12fbf43b6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -146,6 +146,8 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
   case ISD::SHL:
   case ISD::SRA:
   case ISD::SRL:
+  case ISD::ROTL:
+  case ISD::ROTR:
     R = ScalarizeVecRes_BinOp(N);
     break;
   case ISD::FMA: