[PATCH] D85546: [SVE] Add ISD nodes for predicated integer extend inreg operations

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Perhaps I've misunderstood but based on Cameron's original message I suspect he's hit a bug because I lowered all SIGN_EXTEND_INREG operations regardless of the inreg type.  This is wrong because there's no patterns for non-power-of-2 non-byte-based inreg types and thus I guess Cameron has hit a selection failure?

If so then the fix is easy enough, we should expand those cases, which looking at the common code does the correct thing of replacing with shifts. I've create D86394 <https://reviews.llvm.org/D86394>, even if I have misunderstood it fixes a bug anyway.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85546/new/

https://reviews.llvm.org/D85546