[PATCH] D85546: [SVE] Add ISD nodes for predicated integer extend inreg operations

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally added a comment.

Eh, thinking some more, it's still a little weird:

  class SVE_InReg_Extend<ValueType vt, SDPatternOperator op, ValueType pt,
                         ValueType inreg_vt, Instruction inst>
  : Pat<(vt (op pt:$Pg, vt:$Src, inreg_vt, vt:$PassThru)),
        (inst $PassThru, $Pg, $Src)>;

ISD::SIGN_EXTEND_INREG has the same type for the input and output reg, and an additional VT operand to encode the input type.

AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU encodes the input type in the register, and tosses the VT operand.

Maybe it would be better to lower based on the VT operand? That way we don't need to get into the half vector type business (e.g. nxv8i8).


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D85546/new/

https://reviews.llvm.org/D85546