[PATCH] D85546: [SVE] Add ISD nodes for predicated integer extend inreg operations

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

I'm not sure I understand what you think the issue is here.  ISD::SIGN_EXTEND_INREG, AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU, and the SVE sxtb instruction are all the same, as far as I know.  The operand and result types are the same, and the operation in each lane is independent.

By contrast, ISD::ANY_EXTEND does change the element size.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85546/new/

https://reviews.llvm.org/D85546