[PATCH] D85546: [SVE] Add ISD nodes for predicated integer extend inreg operations

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally reopened this revision.
cameron.mcinally added a comment.
This revision is now accepted and ready to land.

These patterns might need attention. ISD::SIGN_EXTEND_INREG expects both the input and output registers to have the same type, extending the small values in place. I.e. the input is unpacked.

But the AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU patterns are expecting to explicitly change the element size. I.e. the input is packed.

I have another patch that's needed to show the problem, but legalize can produce something like this:

      t78: v16i8 = BUILD_VECTOR t217, t216, t215, t214, t213, t212, t211, t210, t209, t208, t207, t206, t205, t204, t203, t202
    t80: v16i16 = any_extend t78
  t82: v16i16 = sign_extend_inreg t80, ValueType:ch:v16i1


Repository:
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https://reviews.llvm.org/D85546